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Cascading PLL Counters to achieve synthesized clock frequencies

Cascading PLL Counters to achieve synthesized clock frequencies


Hi, I am Hui Yin, from Regional Application
Engineering team in Penang. Today I would like to show you on how to how
to utilize Altera PLL IP core to synthesize low frequency output by cascading multiple
counters. I have created a simple project file with
Altera Cyclone V device and I will be using it to show you on how to do the setting in
Altera PLL IP Core graphic user interface to achieve the objective to synthesize low
frequency output with Altera PLL IP core via output counter cascading. If you are using older version of Altera Quartus
II software, the Altera PLL graphic user interface will be available in MegaWizard Plug-in manager. Let me show you on how to output a 10kHz frequency
in the graphic user interface as you can see here. Let’s take a 100MHz frequency as our reference
clock. If you set your desired frequency value directly to the GUI, you will see that the
actual frequency that you can get is 1.17MHz which is the limitation of our Altera PLL
IP core. You will need to enable the physical output
clock parameters to define your M/N and C counter value.
Next, enter a suitable value for your M/N and C counter. When you have entered a wrong
value, you will encounter an error in your message box
as you can see here. For example, I will intentially set the value to 2 which you will see an error
showing that the VCO is out of range. By setting the M counter value to 2, the VCO frequency
that you can get is 200Mhz, which is fall out of the VCO frequency range as shown in
Cyclone V device datasheet here. To achieve the minimum requirement of 600MHz
VCO frequency, set the M counter value to 6 and N counter value to 1. Then, you will need to define a value for
c counter now. You will need to divide the existing 600MHz VCO frequency by 60000 to
achieve the desired 10kHz frequency value. However, you will see that the value of c
counter is out of range. The acceptable value is 1-512 only. In this case, i will set it
to 200. Now, the output frequency of the first counter is 3MHz. Next, change the number of clocks from 1 to
2 in order to create another output counter. Then, make the 1st counter as a cascade counter. Now, on the second counter which is outclk
1 as you can see here, set the c counter value tp 300. Finally, you get the desired value
of 10KHz output frequency as shown here. On behalf of Altera, thank you for watching
this video.


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